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Web of Proceedings - Francis Academic Press
Web of Proceedings - Francis Academic Press

I/O design and FPGA implementation based on DW8051

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DOI: 10.25236/dpaic.2018.012

Author(s)

Bin Zhang, Zhengyan Wang, Yuliang Guo

Corresponding Author

Bin Zhang

Abstract

Based on the IP (Intellectual Property) core DW8051 Core provided by Synopsys, the IO interface (Input/Output Interface) for transmitting data between Core and peripherals is added. The interface is designed and implemented by the hardware description language Verilog HDL as DW8051. A peripheral that is mounted on the DW8051's bus. The design is fully compatible with the Intel 8051 series of microprocessors, which can be controlled by the user program on the DW8051 and verified for correctness on Altera's FPGA chip.

Keywords

DW8051, FPGA, IO Interface, Verilog HDL