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Web of Proceedings - Francis Academic Press

Research Progress of Phase Locked Loop and Delay Locked Loop

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DOI: 10.25236/icmit.2017.64


Zhenda Fu

Corresponding Author

Zhenda Fu


With the development of SoC technology and IP core technology, the Phase Locked Loop (PLL) which is regarded as a basic ASIC macro cell is widely used as a clock generation circuit in wireless communication and microprocessor circuits. The clock generation circuit is mainly composed of PLL or Delay Locked Loop (DLL). This paper first introduces the basic situation of clock deviation and jitter in modern VLSI system concept. Then, the DLL technology used in clock management is introduced, including the fundamental principle and theoretical analysis of PLL and DLL. The circuit of several common DLLs is analyzed and compared with PLL. Finally, the significance of PLL research is summarized.


PLL, DLL, Jitter, clock recovery system, self-biased.