Author(s)

Lin Huang, Wenbiao Peng

Corresponding Author

Lin Huang

Abstract

The design of a fully-integrated 3.125Gbps Ethernet transceiver is described. The circuit adopts parallel structure for both the transmitter and receiver to reduce the speed requirement. The transmitter uses multiphase clock to multiplex the data and current-mode line-driver to drive medium. The receiver uses 1/5-rate parallel-sampling clock and data recovery circuit to facilitate the design and eliminate the need of 1:5 demultiplexer. The circuit was design in 0.18μm CMOS technology. Simulations show that it works well for 3.125Gbps data rate with all process corners.

Keywords

Ethernet; Transmitter; Receiver; Clock Generator; Line Driver; Phase Detector